1. Field of the Invention
The present invention relates to a carry-select adder having adder cells divided into blocks.
2. Description of the Prior Art
Adders are required in many digital logic circuits, such as, digital filters, signal processors and microprocessors. A method for producing an adder is the "ripple-carry" method, wherein a carry output is serially transmitted from an adder cell for a least significant bit to an adder cell for a higher-order bit. The running time of the carry signal will essentially define the addition time.
Another method for producing an adder is the "carry-select" method, in which the adder cells are combined in blocks in an adder and contain double carry paths. Each carry path is used for an assumed carry signal of "0" or "1" at the input side of an adder cell. The carry path to be selected during subsequent data transmissions is decided by a block carry signal, formed from the two individual carry signals of the preceding stage of the block and from the block carry signal of the preceding stage. As a result, the individual carry signals in each block are independent of the carry signal of preceding blocks.
At least two different types of adder cells are required for constructing a "carry-select" adder. One type, an input adder cell is arranged at the beginning of a block, and the input adder cell is followed by an arbitrary number of cells of a second type. Blocks having a higher order in the "carry-select" adder contain a greater number of variable inputs and sum outputs than blocks of lower order. Each individual adder cell in the blocks contains two variable inputs, two carry inputs and outputs, one block carry input and output and a sum output. The number of variable inputs and sum outputs in every block should be selected so that the running time of an individual carry signal through a block corresponds to the sum of the running time of the block carry signals up to this block. In the first stage of a block, the block carry signal is formed from the two carry signals and block carry signal of the last stage of the preceding block. At the input stage of each block, the individual carry signals depend solely on the variable inputs, where the carry inputs can be selectively set to a "high" or a "low" level. The carry signals in a "carry-select" adder pass through each block in parallel by means of two carry paths, where in all adder cells one carry path assumes a low carry signal of "0" at the input of the block, and a second carry path assumes a high carry signal of "1" at the block input. The carry signals in the adder cells depend on the input signals at the variable inputs of the adder cells and on the carry signals at the carry inputs of the adder cells.
German Patent Application EPA-224656 discloses an accelerated run time for the carry signals in an adder circuit. The carry signals are accelerated by alternating connections between adder cells having inverted carry inputs and non-inverted carry outputs alternatively connected with adder cells having non-inverted carry inputs and inverted carry outputs.
German Patent Application DE 33 23 607 discloses a fast adder/subtractor according to the "carry-select" principle. An adder or subtractor having a plurality of stages where the stages are divided into groups that are equipped with two transmission lines. The transmission lines operate with assumed carry levels of "0" or "1" at the input in the least significant stages of the individual groups.
The above referenced adder circuits are disadvantageous due to their excessively slow processing speed.